In a semiconductor memory such as a dynamic random access memory (DRAM), each of the memory cells typically consists of a MOS transistor and a capacitor. As the area occupied by each of the memory cells is reduced, the integration of the memory cells on a semiconductor chip is increased. In general, a reduction in the area occupied by the capacitor results in a decrease in the capacitance of the capacitor. However, it is necessary that the capacitance of the capacitor used in a DRAM is at least 25 fF(femto-Farad).
In order to satisfy the requirement of high integration in the semiconductor memory, various capacitor structures for reducing the area occupied while keeping the capacitance constant have been rapidly developed in recent years. More specifically, capacitors with three-dimensional structures such as the stack capacitor, the cylinder capacitor, and the pin capacitor have been proposed and fabricated.
In IEEE Transactions on Electron Devices, Vol. 38, No. 2, Toru Kaga et al. have disclosed a cylinder capacitor with an extremely high integration, which is effectively applicable to the semiconductor memory, and its manufacturing process. In addition, another cylinder capacitor and its manufacturing process have been disclosed in U.S. Pat. No. 5,866,450. The conventional cylinder capacitors will be described in the following paragraphs with reference to FIGS. 1(a) to 1(c).
FIGS. 1(a) to 1(e) are cross-sectional views showing the process of manufacturing a multi-cylinder capacitor according to the prior art. In FIG. 1(a), a first insulating layer 2 and a second insulating layer 3 are sequentially deposited on a substrate 1 by a conventional Chemical Vapor Deposition (CVD) method. The substrate 1 is provided with a MOS transistor (not shown) before the steps of depositing. Next, through the conventional processes of photolithography and etching, the second insulating layer 3 is selectively etched to form a first opening 4 using the first insulating layer 2 as an etching stop. Then, the first insulating layer 2 is selectively etched to form a second opening 5, having a smaller diameter than that of the first opening 4, for exposing a source/drain region (not shown) of the MOS transistor.
If the first and second insulating layers 2, 3 are made of the same material, then a barrier layer may be deposited on the first insulating layer 2 before the second insulating layer 3 is deposited thereon. The barrier layer serves as the etching stop while the second insulating layer 3 is selectively etched.
In FIG. 1(b), a first polysilicon film 6 is deposited by CVD to fill out the second opening 5 and to cover the first and second insulating layers 2, 3. Thereafter, a third insulating layer 7 such as a silicon oxide layer is deposited on top of the first polysilicon film 6.
Next, as shown in FIG. 1(c), the third insulating layer 7 is selectively etched to form a cylindrical spacer 7a on the sidewall of the first polysilicon film 6, and then a second polysilicon film 8 is deposited over the first polysilicon film 6 and the cylindrical spacer 7a.
Referring to FIG. 1(d), the second polysilicon film 8 is selectively etched to form a second cylindrical electrode 8a next to the cylindrical spacer 7a. Thereafter, the first polysilicon film 6 is etched to form a first cylindrical electrode 6a through a photoresist (not shown) formed over the opening 4, and then the photoresist is removed.
At last, referring to FIG. 1(e), the cylindrical spacer 7a and the second insulating layer 3 are removed by selective etching, and a multi-cylinder capacitor, specifically a double-cylinder capacitor, according to the prior art is achieved.
It is possible to increase the total surface area of the electrodes of the capacitor without reducing the integration of the semiconductor memory due to the presence of the cylindrical portion of the multi-cylinder capacitor. Therefore, the multi-cylinder capacitor is a good candidate for the advanced semiconductor memory with a very large integration.
However, the manufacturing processes of the multi-cylinder capacitor disclosed in IEEE Transactions on Electron Devices, Vol. 38, No. 2 and U.S. Pat. No. 5,866,450 are complicated because in using them to manufacture the capacitor it is necessary to deposit the third insulating layer 7 and to form the cylindrical spacer 7a by selectively etching the third insulating layer 7. If more cylindrical electrodes are required to further increase the total surface area of the electrodes of the capacitor due to the application of the high-density MOS memory, then the complicated nature of the process for manufacturing the multi-cylinder capacitor according to the prior art is more apparent. In other words, a step for depositing a forth insulating layer and a step for selectively etching the forth insulating layer to form a second cylindrical spacer are both additionally required if a three-cylinder capacitor is formed. Therefore, in accordance with the prior art, two additional steps are necessary for increasing the number of cylindrical electrode of the multi-cylinder capacitor by one. This increase in manufacturing steps causes a reduction in the reliability of the multi-cylinder capacitor and an increase in the cost of production.